Monday 15 July 2013

Design of 4 : 1 Multiplexer using Conditional Operator (Verilog Code).



Design of 4 : 1 Multiplexer using Conditional Operator (Data Flow Modeling Style).

Output Waveform : 4 : 1 Multiplexer

Verilog CODE-




//-----------------------------------------------------------------------------
//
// Title       : multiplexer4_1
// Design      : verilog upload
// Author      : Naresh Singh Dobal
// Company     : nsd
//
//-----------------------------------------------------------------------------
//
// File        : 4 to 1 multiplexer using conditional operator.v



module multiplexer4_1 ( din ,sel ,dout );

output dout ;

input [3:0] din ;
input [1:0] sel ;


assign dout = (sel==2'b00) ? din[3] :
 (sel==2'b01) ? din[2] :
 (sel==2'b10) ? din[1] :
 din[0];

endmodule



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