Design of 4 Bit Adder cum Subtractor using Loops (Behavior Modeling Style) (verilog Code) -

Design of 4 Bit Adder cum Subtractor using Loops (Behavior Modeling Style) -

Output Waveform :    4 Bit Adder cum Subtractor

Verilog CODE -



//-----------------------------------------------------------------------------
//
// Title       : adder_subtractor_4bit
// Design      : verilog upload 4
// Author      : Naresh Singh Dobal
// Company     : nsdobal@gmail.com
// Verilog Programs & Exercise with Naresh Singh Dobal
//
//-----------------------------------------------------------------------------
//
// File        : Design of 4 Bit adder cum subtractor.v


module adder_subtractor_4bit ( a ,b ,sel ,dout );

output [3:0] dout ;
reg [3:0] dout ;

input [3:0] a ;
wire [3:0] a ;
input [3:0] b ;
wire [3:0] b ;
input sel ;
wire sel ;

reg [4:0] s;
wire [3:0] l;

integer i;

assign l = b ^ {sel,sel,sel,sel};

always @ (a or b or sel) begin
s[0] = sel;
for (i=0;i<=3;i=i+1) begin
dout[i] = a[i] ^ l[i] ^ s[i];
s[i+1] = (a[i] & l[i]) | (l[i] & s[i]) | (s[i] & a[i]);
end
end


endmodule