Design of D-Latch using Behavior Modeling Style (Verilog CODE) -

Design of D-Latch using Behavior Modeling Style -

Output Waveform :   D  Latch

Verilog CODE -



//-----------------------------------------------------------------------------
//
// Title       : D_latch
// Design      : verilog upload 2
// Author      : Naresh Singh Dobal
// Company     : nsdobal@gmail.com
// Verilog Programs & Exercise by Naresh Singh Dobal.
//
//-----------------------------------------------------------------------------
//
// File        : D Latch using Behavior Modeling Style.v


module D_latch ( enable ,din ,reset ,dout );

output dout ;
reg dout ;

input enable ;
wire enable ;
input din ;
wire din ;
input reset ;
wire reset ;

always @ (enable or din or reset) begin
if (reset)
dout = 0;
else begin
if (enable)
dout = din;
end
end

endmodule