Sunday, 28 July 2013

Design of Parallel IN - Serial OUT Shift Register using Behavior Modeling Style (Verilog CODE).

Design of Parallel In - Serial OUT Shift Register using Behavior Modeling Style -

Output Waveform :  Parallel IN - Serial OUT Shift Register

Verilog CODE -

// Title       : parallel_in_serial_out
// Design      : vhdl_upload2
// Author      : Naresh Singh Dobal
// Company     :
// Verilog HDL Programs &  Exercise with Naresh Singh Dobal.
// File        : Parallel IN -  Serial OUT Shift Register.v

module parallel_in_serial_out ( din ,clk ,reset ,load ,dout );

output dout ;
reg dout ;

input [3:0] din ;
wire [3:0] din ;
input clk ;
wire clk ;
input reset ;
wire reset ;
input load ;
wire load ;

reg [3:0]temp;

always @ (posedge (clk)) begin
if (reset)
temp <= 1;
else if (load)
temp <= din;
else begin
dout <= temp[3];
temp <= {temp[2:0],1'b0};



Manasa Hegde said...

plzz give the testbench code for this...

ANIL KUMAR said...

plzz write the same code to run for 8 times

Uday Arun said...

Pl. correct the code. When reset signal is high then temp variable should be loaded with Zero not one.

ABHIJEET said...

would you please explain why temp <= {temp[2:0],1'b0}; line is used.

srikant karwa said...
This comment has been removed by the author.
srikant karwa said...

see it,temp is operating left shift and input is given zero in 0th position.

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