VLSI Major Classification (Front End and Back End Design) -
|VLSI Major Classification (Learn Verilog HDL with Naresh Singh Dobal series).|
VLSI Industry, - VLSI is mainly divided into two major domains, first one is called VLSI Front End and second is VLSI Back End, As I told you previously that this series is designed according to the practical approaches, labs and works, so I am not going into deep, But you must differentiate these two domain to plan your career in better way, The major different between them are –
VLSI Front end considers all the logical designing and verification part, In simple words we can say all the work up to the Gate level or RTL Level designing and verification considered as VLSI Front End Designing and Verification, We have multiple ways for logical designing of IC (Integrated Circuits)’s in VLSI Front End, For Example in early days when we have very less chip complexity, designers used Manual Logical Designing and they used concept of number system, Basic Gates Concept, K-maps, Boolean Mathematics, expression handling etc.
As the time passed and according to the Moore's law chip complexity has been increased by multiple times and at that level logical designing was not manageable using manual designing, So Schematics based Designing was discovered, and we started work on computers and simulators, and We design our systems using Pick and Place concept. In this concept we have some type of tool bars and all the basic components and elements like basic gates, multiplexer, ALU, flip flops was defined in the tool bars with there properties and user just pick that component from the list and place it into the computer screen and then route all the components with the help of wires. But at this level one thing is common and this is designing methods, Using this concept we only optimized the verification concept and this saved a lot of time and money. Because verification needed more than twice of efforts (in term of time and money) as compare to designing.
But again these things failed as the chip complexity increased, So researchers invented a totally different concept of designing and verification. And that concept was HDL Based Designing and Verification. And that concept was perfectly suited at that time for complex chip design (or high density chips). These things reduces the Designing Time and Cost and mainly the verification time.
But now again HDL based designing is exactly where, as the schematic based designing is as before 15 years, because in now a days hundreds of pages of codes are not uncommon and this is really very difficult to handle and manage designs and verification plans. So now the question is What Will be the next ????????
Second is VLSI Back End, that consider all the designing and verification part after logical designing means Gate level or RTL level designing, That may include Floor Planning, Place & Route, and All the foundry work like fabrication, packaging etc. are also comes in VLSI Back End.
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