Tuesday, 16 July 2013

Small Description about Gate Level Modeling Style in Verilog HDL.




Small Description about Gate Level Modeling Style in Verilog HDL.


Structural Modeling Style -

Structural Modeling Style shows the Graphical Representation of modules/ instances / components with their Interconnection. 
In Structural Modeling Style We defines that how our Components / Registers / Modules are Connected to each other using Nets/ Wires.

  • Structural Modeling Style works on Concurrent Executions. 

Syntax -


Instance_name       Component_name     (Association List) ;



  • Component_label can be any legal identifier and considered as the name of the instance.
  • Instance_name must be the name of a pre-designed module.


Methods of Component Instantiations -

  • Positional Mapping.
  • Nominal Mapping.


Positional Mapping. -   

Example -

dff     u0    (clk  ,   reset    ,   din   ,    dout );


Sequence of Formal ports must be same with sequence of Actual Ports of component.



Nominal Mapping -

Example -

dff     u0     ( .clk (clk)   ,  
                    .reset  ( reset)    ,
                    .din (din),
                    .dout (dout) )   ;


No need to consider the sequence of Formal ports and Actual Ports.





Sample Programs-





Flip Flop Designs using Structural Modeling Style-



Shift Registers Design using Structural Modeling Style-




  • 4 - Bit Stack Design using Structural Modeling Style (Verilog Code).
  • 4 - Bit Queue Design using Structural Modeling Style (Verilog Code).


2 comments :

Gokul Ravindran said...

can you help me with verilog code for finding out the multiplicative inverse of a number??

Mahesh Upadhyay said...

nice

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