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10 comments :

tajmul said...

how i design a BCD adder using behavioral modeling in verilog??? please send me the solution in my e-mail (tajmul.eee.cuet@gmail.com)..

with thanks
Kazi Tajmul Islam

SAMIR said...

how can i design a floating point subtraction confirming to ieee standards using verilog hdl...i want the code

Naveen Kumar said...

i want to model a COntent addressable memory of depth 8 words.... i know how to perform the read and write operation but iam in a wrong way of performing the searching operation to get a match signal as output...
so Give me suggestions...!?

somnath chaurasiya said...

sir how can i design a mux 16:1 by using mux 4:1 through structure modeling.

Kamenashi elric said...
This comment has been removed by the author.
Kamenashi elric said...

Sir could you post a system verilog source code and test bench for car park control system? thank you contact me lc40lc73@gmail.com thank you.

Unknown said...

sir could you help me with the convolution code in verilog by simply taking two 3*3 matrices as inputs. i am facing problem in defining multi dimentional array to give matrix as a input. please kindly reply me back

Goondla Suresh said...
This comment has been removed by the author.
Goondla Suresh said...

Sir can i have the HDL code for FPGA based homeautomation? here is my mail id: suresh.goondla@gmail.com and contact number 9985464243

Mateo said...

Sir Naresh cam you send me the code of the project of the control of temperature? thanks i apreciate it my emal is mateofonseca0823@gmail.com

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